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performance motion devices, inc. 55 old bedford rd lincoln, ma 01773 magellan? motion processor mc58000 electrical specification for brushed servo, brushless servo, microstepping and stepping motion control preliminary revision 0.6, november 2003
notice this document contains proprietary and confidential information of performance motion devices, inc., and is protected by federal co pyright law. the contents of this document may not be disclosed to third parties, translated, copied, or duplicated in any form, in whole or in part, without the express written permission of pmd. the information contained in this document is subject to change without notice. no part of this document may be reproduced or transmitted in an y form, by any means, electronic or mechanical, for any purpose, without the express written permission of pmd. copyright 2003 by performance motion devices, inc. magellan and c-motion are trademarks of performance motion devices, inc
mc58000 electrical specification ? preliminary 11/13/2003 iii warranty pmd warrants performance of its products to the specifications applicable at the time of sale in accordance with pmd's standard wa rranty. testing and other quality control techniques are utilized to the extent pmd deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. performance motion devices, inc. (pmd) reserves th e right to make changes to its products or to discontinue any product or service without notice, and advises customers to obtain the latest version of relevant information to verify, before placin g orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. safety notice certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage. products are not designed, authorized, or warranted to be suitable for use in life support devices or systems or other critical applications. inclusion of pmd products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the cust omer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent procedural hazards. disclaimer pmd assumes no liability for applic ations assistance or cu stomer product design. pmd does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual pr operty right of pmd covering or relating to any combination, machine, or process in which such prod ucts or services might be or are used. pmd's publication of information regarding any third party's products or services does not constitute pmd's approval, warranty or endorsement thereof.
mc58000 electrical specification ? preliminary 11/13/2003 iv
mc58000 electrical specification ? preliminary 11/13/2003 v related documents mc50000 motion processor user?s guide (mc50000ug) how to set up and use all members of the mc50000 motion processor family. mc50000 motion processor programmer ?s command reference (mc50000pr) descriptions of all mc50000 motion processor commands, with coding syntax and examples, listed alphabetically for quick reference. mc50000 motion processor el ectrical specifications three booklets containing physical and electrical characteristics, timing diagrams, pinouts, and pin descriptions of each: mc55000 series, for stepping motion control (mc55000es); mc58000 series, for brushed and brushless se rvo, microstepping and stepping motion control (mc58000es). mc50000 motion processor developer?s kit manual (dk50000m) how to install and configure the dk50000 developer?s kit pc board.
mc58000 electrical specification ? preliminary 11/13/2003 vi
mc58000 electrical specification ? preliminary 11/13/2003 vii table of contents warranty....................................................................................................................... ............................... iii safety notice .................................................................................................................. .............................. iii discla imer..................................................................................................................... ................................ iii related do cuments.............................................................................................................. ......................... v table of contents.............................................................................................................. .......................... vii 1 the mc5000 0 fam ily........................................................................................................... ..................... 9 1.2 how to order................................................................................................................... ............. 11 2 functional characteristics................................................................................................... ................... 12 2.1 configurations, paramete rs, and performance .............................................................................. 12 2.2 physical characteristics and mounting dimensions....................................................................... 15 2.2.1 cp chip ........................................................................................................................ ......... 15 2.2.2 io chip ........................................................................................................................ .......... 16 2.3 environmental and electrical ratings ........................................................................................... .17 2.4 mc58110 system configuration ? si ngle chip, 1 axis control ..................................................... 17 2.5 mc58020 system configuration ? tw o chip, 1 to 4 axis control ................................................. 18 2.6 peripheral device address mapping.............................................................................................. .19 3 electrical char acteristics................................................................................................... ..................... 20 3.1 dc charact eristic s............................................................................................................. ............ 20 3.2 ac charact eristic s............................................................................................................. ............ 20 4 i/o timing diagrams .......................................................................................................... .................... 23 4.1 clock .......................................................................................................................... .................. 23 4.2 quadrature encoder input ....................................................................................................... ...... 23 4.3 reset .......................................................................................................................... ................... 23 4.4 host interface, 8/16 mode...................................................................................................... ....... 24 4.4.1 instruction write, 8/16 mode................................................................................................. 24 4.4.2 data write, 8/16 mode.......................................................................................................... .24 4.4.3 data read, 8/16 mode........................................................................................................... .25 4.4.4 status read, 8/16 mode......................................................................................................... .25 4.5 host interface, 16/16 mode..................................................................................................... ...... 26 4.5.1 instruction write, 16/16 mode............................................................................................... 26 4.5.2 data write, 16/16 mode......................................................................................................... 26 4.5.3 data read, 16/16 mode.......................................................................................................... 27 4.5.4 status read, 16/16 mode........................................................................................................ 27 4.6 external memory timing......................................................................................................... ...... 28 4.6.1 external memory read........................................................................................................... 28 4.6.2 external memo ry write ......................................................................................................... 2 9 4.7 peripheral device timing ....................................................................................................... ........ 30 4.7.1 peripheral device read......................................................................................................... .. 30 4.7.2 peripheral device write ........................................................................................................ .31 5 pinouts and pi n descriptions................................................................................................. ................. 32 5.1 pinouts for th e mc58 110 ........................................................................................................ ..... 32 5.1.1 mc58110 cp chip pi n description........................................................................................ 33
mc58000 electrical specification ? preliminary 11/13/2003 viii 5.1.2 mc58110 cp chip pin assignmen t for multiple motor types................................................ 37 5.2 pinouts for th e mc58 420 ........................................................................................................ ..... 38 5.2.1 mc58020 io chip pi n description ........................................................................................ 39 5.2.2 mc58020 io chip pin assignmen t for multiple motor types ................................................ 44 5.2.3 mc58020 cp chip pi n description........................................................................................ 46 5.3 external osc illator f ilter ..................................................................................................... ........... 50
mc58000 electrical specification ? preliminary 11/13/2003 9 1 the mc50000 family mc55020 series mc58020 series mc55110 mc58110 number of axes 4,3,2 or 1 4,3,2 or 1 1 1 number of chips 2 (cp and io) 2 (cp and io) 1 (cp) 1 (cp) motor type stepping brushed dc servo brushless dc servo stepping stepping brushed dc servo brushless dc servo stepping output format pulse and direction brushed single phase sinusoidal commutation microstepping pulse and direction pulse and direction brushed single phase sinusoidal commutation microstepping pulse and direction communication interface parallel asynchronous serial can 2.0b position input incremental encoder input parallel word device input index & home signals position capture directional limit switches motor command output pwm output - - parallel dac output - - spi dac output - - trajectory generation pulse & direction output trapezoidal profiling s-curve profiling velocity profiling electronic gearing on-the-fly changes servo filter pid position loop - - dual encoder loop - - derivative sampling time - - feedforward (accel & vel) - - dual bi-quad filter - -
mc58000 electrical specification ? preliminary 11/13/2003 10 mc55020 series mc58020 series mc55110 mc58110 miscellaneous data trace/diagnostics motion error detection (with encoder) (with encoder) axis settled indicator (with encoder) (with encoder) analog input programmable bit output software-invertible signals user-defined i/o external ram support multi-chip synchronization chipset part numbers mc55120 mc55220 MC55320 mc55420 mc58120 mc58220 mc58320 mc58420 mc55110 mc58110 developer's kit p/n's: dk55420 dk58420 dk55110 dk58110 introduction this manual describes the operational characterist ics of the mc58000 series motion processors from pmd. these devices are members of pmd?s third-generation motion processor family. each of these devices is a complete chip-based motion processor. they provide trajectory generation and related motion control functions. depending on the type of motor controlled they provide servo loop closure, on-board commutation for brushless motors, and high-speed pulse and direction outputs. together these products provide a software-compatible family of dedicated motion processors that can handle a large variety of system configurations. each of these chips utilize a similar architecture, consisting of a high-speed computation unit, along with an asic (application specific integrated circ uit). the computation unit contains special on- board hardware that makes it well suited for the task of motion control. along with similar hardware architecture these ch ips also share most soft ware commands, so that software written for one series ma y be re-used with another, even though the type of motor may be different.
mc58000 electrical specification ? preliminary 11/13/2003 11 family summary mc55000 series ? these chipsets provide high-speed puls e and direction signals for step motor systems. for the mc55020 series two tqfp ics ar e required: a 100-pin input/output (io) chip, and a 144-pin command processor (cp) chip, while the mc55110 has all functions integrated into a single chip a 144-pin comma nd processor (cp) chip. mc58000 series ? this series outputs motor comman ds in sign/magnitude pwm or dac- compatible format for use with dc-brush motors or brushless dc motors having external commutation; two-phase or three-phase sinusoidally commutated motor signals in pwm or dac- compatible format for brushless servo motors; puls e and direction output for step motors; and two phase signals per axis in either pwm or da c-compatible signals for microstepping motors. for the mc58020 series two tqfp ics are required: a 100-pin input/output (io) chip, and a 144- pin command processor (cp) chip , while the mc58110 has all functions integrated into a single 144- pin cp chip. 1.2 how to order when ordering a single-chip configuration, only the cp part number is necessary. for two-ic and multi-axis configurations, both the cp and the io part numbers are required. mc5 0cp . cp (1 or 2 chip configurations) motor type 8 = multi motor 5 = pulse & direction # axes 1,2,3,4 # chips 1 (cp only) 2 (cp & io) cp version (call pmd) mc50000io io (2 chip configurations only) dk5 0cp . 50000io developer?s kit motor type 8 = multi motor 5 = pulse & direction # axes 1,2,3,4 # chips 1 (cp only) 2 (cp & io) cp version (call pmd)
mc58000 electrical specification ? preliminary 11/13/2003 12 2 functional characteristics 2.1 configurations, parameters, and performance configuration 4 axes (mc58420) 3 axes (mc58320) 2 axes (mc58220) 1 axis (mc58120 or mc58110) operating modes servo closed loop (motor command is driven from output of servo filter) open loop (motor command is driven from user-programmed register) microstepper open loop (motor command is driven from out put of trajectory generator & microstep generator, encoder input used for stall detection) stepper open loop (pulse generator is driven by tr ajectory generator output, encoder input used for stall detection) communication modes 8/16 parallel 8 bit external parallel bus with 16 bit command word size 16/16 parallel 16 bit external parallel bus with 16 bit command word size point to point asynchronous serial multi-drop asynchronous serial can bus 2.0b, protocol co-exists with canopen serial port baud rate range 1,200 baud to 416,667 baud profile modes s-curve point-to-point velocity, acceleration, jerk, and position parameters trapezoidal point-to-point velocity, acceleration, deceleration, and position parameters velocity-contouring velocity, acce leration, and deceleration parameters electronic gear encoder or trajecto ry position of one axis used to drive a second axis. master and slave axes and gear ratio parameters external all commanded profile parameters are generated by the host and stored in external ram position range -2,147,483,648 to +2,147,483,647 counts|steps velocity range -32,768 to +32,767 counts|steps per cycle with a resolution of 1/65,536 counts|steps per cycle acceleration and deceleration ranges 0 to +32,767 counts|steps per cycle 2 with a resolution of 1/65,536 counts|steps per cycle 2 jerk range 0 to ? counts|steps per cycle 3 with a resolution of 1/4,294,967,296 counts|steps per cycle 3 electronic gear ratio range -32,768 to +32,767 with a resolution of 1/65,536 (negative and positive direction)
mc58000 electrical specification ? preliminary 11/13/2003 13 filter modes scalable pid + velocity feedforward + acceleration feedforward + bias. also includes integration limit, settable derivative sampling time, output motor command limiting and two bi-quad filters dual encoder feedback mode where auxiliary encoder is used for backlash compensation filter parameter resolution 16 bits position error 32 bits position error tracking motion error window allows axis to be stopped upon exceeding programmable window tracking window allows flag to be set if axis exceeds a programmable position window axis settled allows flag to be set if axis exceeds a programmable position window for a programmable amount of time after trajectory motion is compete motor output modes pwm (10-bit resolution at 20 khz or 8-bit resolution at 80 khz) parallel dac-compatible (16 bits) spi dac-compatible (16 bits) step and direction (4.98 mpulses/sec maximum) commutation rate 10khz microstepping waveform sinusoidal microsteps per full step programmable, 1 to 256 maximum encoder rate incremental (up to 10 mcounts/sec) parallel-word (up to 160 mcounts/sec) parallel encoder word size 16 bits parallel encoder read rate 20 khz (reads all axes every 50 sec) hall sensor inputs 3 hall effect inputs per axis (ttl level signals) cycle/servo loop timing range 51.2 microseconds to 1.048576 seconds minimum cycle/servo loop time 51.2 microseconds multi-chip synchronization <10 sec difference between master and slave servo cycle limit switches 2 per axis: one for each direction of travel position-capture triggers 2 per axis: index and home signals other digital signals (per axis) 1 axisin signal per axis, 1 axisout signal per axis software-invertable signals encoder a, encoder b, index, home, axis in, axisout, positivelimit, negativelimit, halla, hallb, hallc (all indivi dually programmable per axis) analog input 8 10-bit analog inputs user defined discrete i/o 256 16-bit wide user defined i/o ram/external memory support 65,536 blocks of 32,768 16 bit words per block. total accessible memory is 2,147,483,648 16 bit words trace modes one-time continuous maximum number of trace variables 4 number of traceable variables 27
mc58000 electrical specification ? preliminary 11/13/2003 14 number of host instructions 154
mc58000 electrical specification ? preliminary 11/13/2003 15 2.2 physical characteristics and mounting dimensions 2.2.1 cp chip all dimensions are in millimeters.
mc58000 electrical specification ? preliminary 11/13/2003 16 2.2.2 io chip all dimensions are in millimeters.
mc58000 electrical specification ? preliminary 11/13/2003 17 2.3 environmental and electrical ratings storage temperature (t s ) -65 c to 150 c operating temperature: standard (t a ) -40 c to 85 c* operating temperature: extended (t a ) -40 c to 125 c* power dissipation (p d ) cp 445 mw io 110 mw nominal clock frequency (f clk ) 40.0 mhz supply voltage limits (v cc ) -0.3v to +4.6v supply voltage operating range (v cc ) 3.0v to 3.6v 2.4 mc58110 system configuration ? single chip, 1 axis control the following figure shows the principal co ntrol and data paths in an mc58110 system. host cp hostdata0-15 ~hostslct parallel port 40 mhz clock hostrdy ~hostwrite hostcmd ~hostread external memory user i/o parallel communication pld/fpga 2 0 m h z c l o c k 16 bit data/address bus axisout negative positive axisin limit switches hall a/b/c motor amplifier pwm output d a c o u t p u t d/a converter a home index b encoder hostintrpt serial network canopen/can 2.0b network spi serial port configuration can bus configuration parallel word input motor type configuration analog inputs the shaded area shows the cpld /fpga that must be provided by the designer if parallel communication is required. a description and the n ecessary logic (in the form of schematics) of this device are detailed in the section pa rallel fpga section of this manual.
mc58000 electrical specification ? preliminary 11/13/2003 18 the cp chip is a self-contained motion processor. in addition to handling a ll system functions, the cp chip contains the profile generator, which calcul ates velocity, acceleration, and position values for a trajectory. when an axis is configured for serv o motor control, a digital servo filter controls the motor output signal. when an axis is configured for microstepping motor control, a commutator controls the motor output signal. in either case , one of three types of output can be generated: ? a pulse-width modulated (pwm) signal output; or ? a dac-compatible value routed via the data bus to the appropriate d/a converter; or ? a dac-compatible value routed via the spi port to the appropriate d/a converter when an axis is configured for st ep motor control, the cp chip gene rates step and direction signals. axis position information returns to the motion processor in the form of encoder feedback using either the incremental encoder input signals, or via the bus as parallel word input. the mc58110 can co-exist in a canopen network as a slave device. it is can 2.0b compliant. 2.5 mc58020 system configuration ? two chip, 1 to 4 axis control the following figure shows the principal co ntrol and data paths in an mc58020 system. host io cp hostdata0-15 ~hostslct parallel port 40 mhz clock hostintrpt 20mhz clock hostrdy ~hostwrite hostcmd ~hostread serial network axisout negative positive axisin limit switches motor amplifier a home index b encoder pwm or s+d output analog inputs external memory other user devices 16-bit data bus d a c o u t p u t d/a converter user i/o serial port configuration can bus configuration parallel word input hall a/b/c canopen/can 2.0b network spi motor type configuration
mc58000 electrical specification ? preliminary 11/13/2003 19 the io chip contains the parallel host interface, the incremental encoder input along with motor output signals that are configured as pwm or step and direction signals according to the motor type selected for each axis. the cp chip contains the profile generator, wh ich calculates velocity, acceleration, and position values for a trajectory. when an axis is configur ed for servo motor control, a digital servo filter controls the motor output signal. when an axis is configured for microstepping motor control, a commutator controls the motor output signal. in either case, one of three types of output can be generated: ? a pulse-width modulated (pwm) signal output; or ? a dac-compatible value routed via the data bus to the appropriate d/a converter; or ? a dac-compatible value routed via the spi port to the appropriate d/a converter when an axis is configured for step motor control, the io chip generates the step and direction signals. axis position information returns to the motion processor in the form of encoder feedback using either the incremental encoder input signals, or via the bus as parallel word input. the mc58020 can co-exist in a canopen network as a slave device. it is can 2.0b compliant. 2.6 peripheral device address mapping device addresses on the cp chip?s external bus are memory-mapped to th e following locations: address device description 0100h motor type configuration contains the configuration data for the per axis motor type selection 0200h serial port configuration contains the configuration data (transmission rate, parity, stop bits, etc) for the asynchronous serial port 0400h can port configuration contains the configuration data (baud rate and node id) for the can controller 0800h parallel-word encoder base addre ss for parallel-word feedback devices 1000h user-defined base address for user-defined i/o devices 2000h ram page pointer page po inter to external memory 4000h motor-output dacs base addre ss for motor-output d/a converters 8000h reserved
mc58000 electrical specification ? preliminary 11/13/2003 20 3 electrical characteristics 3.1 dc characteristics (v cc and t a per operating ratings, f clk = 40.0 mhz) symbol parameter minimum maximum conditions v cc supply voltage 3.00 v 3.6 v i dd supply current 135 ma cp 33 ma io open outputs input voltages v ih logic 1 input voltage 2.0 v v cc @cp v il logic 0 input voltage 0.8 v @cp output voltages v oh logic 1 output voltage 2.4 v -2 ma@cp v ol logic 0 output voltage 0.4 v 8 ma@cp other i out tri-state output leakage current -2 a 2 a @cp 0 < v out < v cc i in input current -25 a 25 a @cp 0 < v i < v cc i inclk input current, cpclk -25 a 25 a 0 < v i < v cc c io input/output capacitance 2/3 pf @cp typical analog input z ai analog input source impedance 10 ? e dnl differential nonlinearity error. difference between the step width and the ideal value. -1 2 lsb e inl integral nonlinearity error. maximum deviation from the best straight line through the adc transfer characteristics, excluding the quantization error. 2 lsb 3.2 ac characteristics see timing diagrams, section 4, for tn numbers. the symbol ? ~ ? indicates active low signal. timing interval tn minimum maximum clock frequency (f clk ) 4 mhz 40 mhz (note 1) clock pulse width t1 20 nsec 30 nsec clock period (note 3) t2 50 nsec 250 nsec encoder pulse width t3 150 nsec dwell time per state t4 75 nsec
mc58000 electrical specification ? preliminary 11/13/2003 21 timing interval tn minimum maximum index setup and hold (relative to quad a and quad b low) t5 0 nsec ~hostslct hold time t6 0 nsec ~hostslct setup time t7 0 nsec hostcmd setup time t8 0 nsec hostcmd hold time t9 0 nsec read data access time t10 25 nsec read data hold time t11 10 nsec ~hostread high to hi-z time t12 20 nsec hostrdy delay time t13 100 nsec 150 nsec ~hostwrite pulse width t14 70 nsec write data delay time t15 15 nsec write data hold time t16 0 nsec read recovery time (note 2) t17 60 nsec write recovery time (note 2) t18 60 nsec read pulse width t19 70 nsec external memory read timing clockout low to control valid t20 4 nsec clockout low to address valid t21 8 nsec address valid to ~readenable low t22 31 nsec clockout high to ~readenable low t23 5 nsec data access time from address valid t24 40 nsec data access time from ~readenable low t25 31 nsec data hold time t26 0 nsec clockout low to control inactive t27 5 nsec address hold time after clockout low t28 2 nsec clockout low to strobe low t29 5 nsec clockout low to strobe high t30 6 nsec w/~r low to r/~w rising delay time t31 5 nsec external memory write timing clockout high to control valid t32 4 nsec clockout high to address valid t33 10 nsec address valid to ~writeenable low t34 29 nsec clockout low to ~writeenable low t35 6 nsec data setup time before ~writeenable high t36 33 nsec data bus driven from clockout low t37 -3 nsec data hold time t38 2 nsec clockout high to control inactive t39 5 nsec address hold time after clockout low t40 -5 nsec clockout low to strobe low t41 6 nsec clockout low to strobe high t42 6 nsec r/~w low to w/~r rising delay time t43 5 nsec clockout high to control valid t44 6 nsec peripheral device read timing address valid to ~readenable low t22-45 56 nsec data access time from address valid t24-46 65 nsec data access time from ~readenable low t25-47 56 nsec
mc58000 electrical specification ? preliminary 11/13/2003 22 timing interval tn minimum maximum peripheral device write timing address valid to ~writeenable low t34-48 54 nsec data setup time before ~writeenable high t36-49 58 nsec device ready/ outputs initialized t57 1 msec note 1 performance figures and timing information valid at f clk = 40.0 mhz only. for timing information and performance parameters at f clk < 40.0 mhz, contact pmd. note 2 for 8/16 interface modes only. note 3 the clock low/high split has an allowable range of 40-60%.
mc58000 electrical specification ? preliminary 11/13/2003 23 4 i/o timing diagrams for the values of tn , please refer to the table in section 3.2. 4.1 clock t1 t2 masterclkin t1 4.2 quadrature encoder input t3 t3 t4 t4 t5 (= ~quada * ~quadb * ~index) t5 index quad a quad b ~index 4.3 reset v cc i/oclk ~reset t50 t57
mc58000 electrical specification ? preliminary 11/13/2003 24 4.4 host interface, 8/16 mode 4.4.1 instruction write, 8/16 mode hostdata0-7 ~hostslct hostcmd hostrdy ~hostwrite note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. t7 t6 see note t8 t18 t9 t14 t14 see note t16 t16 t15 t13 t15 low byte high byte 4.4.2 data write, 8/16 mode hostdata0-7 ~hostslct hostcmd hostrdy ~hostwrite note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. t7 t8 t6 t9 t15 see note see note low byte t16 t13 t16 t15 high byte t18 t14 t14
mc58000 electrical specification ? preliminary 11/13/2003 25 4.4.3 data read, 8/16 mode hostdata0-7 ~hostslct t7 t8 t19 t6 t9 t13 t11 hostcmd hostrdy ~hostread t12 t10 high-z high-z high-z high byte low byte note: if setup and hold times are met, ~hostslct and hostcmd may be de-asserted at this point. see note see note 4.4.4 status read, 8/16 mode ~hostslct t7 t8 t17 t6 t9 t11 hostcmd hostdata0-7 ~hostread t12 t10 high-z high-z high-z high byte low byte t19
mc58000 electrical specification ? preliminary 11/13/2003 26 4.5 host interface, 16/16 mode 4.5.1 instruction write, 16/16 mode t7 t6 t9 t14 t16 t8 t13 t15 ~hostslct hostcmd ~hostwrite hostdata0-15 hostrdy 4.5.2 data write, 16/16 mode t7 t6 t9 t14 t16 t8 t13 t15 ~hostslct hostcmd ~hostwrite hostdata0-15 hostrdy
mc58000 electrical specification ? preliminary 11/13/2003 27 4.5.3 data read, 16/16 mode ~hostslct t7 t8 t13 t11 hostcmd hostdata0-15 hostrdy ~hostread t12 t10 high-z high-z t6 t9 t19 4.5.4 status read, 16/16 mode ~hostslct t7 t8 t11 hostcmd hostdata0-15 ~hostread t12 t10 high-z high-z t6 t9 t19
mc58000 electrical specification ? preliminary 11/13/2003 28 4.6 external memory timing 4.6.1 external memory read note: pmd recommends using memory with an access time no greater than 15 nsec. ~ramslct addr0-addr15 ~readenable data0-data15 t24 t20 ~strobe clockout t21 t27 t30 t29 t22 t25 t26 t28 t23 w/~r r/~w t31
mc58000 electrical specification ? preliminary 11/13/2003 29 4.6.2 external memory write ~ramslct addr0-addr15 r/~w ~writeenable data0-data15 t36 t32 ~strobe w/~r clockout t33 t43 t39 t42 t41 t34 t38 t40 t35 t37 t44
mc58000 electrical specification ? preliminary 11/13/2003 30 4.7 peripheral device timing 4.7.1 peripheral device read ~periphslct addr0-addr15 ~readenable data0-data15 t46 t20 ~strobe clockout t21 t27 t30 t29 t45 t47 t26 t28 t23 w/~r r/~w t31
mc58000 electrical specification ? preliminary 11/13/2003 31 4.7.2 peripheral device write ~periphslct addr0-addr15 r/~w ~writeenable data0-data15 t49 t32 ~strobe w/~r clockout t33 t43 t39 t42 t41 t48 t38 t40 t35 t37 t44
mc58000 electrical specification ? preliminary 11/13/2003 32 5 pinouts and pin descriptions 5.1 pinouts for the mc58110 cp ~readenable ~periphslct 127 130 132 134 136 138 143 5 9 13 15 17 20 22 24 27 80 78 74 71 68 64 61 57 53 51 48 45 43 39 34 31 25 26 72 70 123 srlxmt srlrcv canxmt/srlenable canrcv masterclkin data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 92 120 82 87 133 r/~w ready ~ramslct ~reset 19 93 46 38 poslim1 neglim1 115 114 117 32 16 axisout1 axisin1 analogvcc analogrefhigh analogreflow analoggnd 116 hall1a hall1b hall1c 18 14 37 w/~r ~hostinterrupt 131 synch 21 vssf 12 oscfilter1 11 oscfilter2 10 vcc5 58 vcc 4, 29, 42, 50, 67, 77, 86, 95, 122, 129, 141 112 113 110 111 107 109 105 108 analog0 analog1 analog2 analog3 analog4 analog5 analog6 analog7 35 30 spiclock spixmt gnd 3, 28, 41, 49, 66, 76, 85, 94, 125, 128, 140 no connection 1, 2, 6, 7, 33, 36, 55, 59, 60, 62, 63, 65, 84, 90, 91, 97, 118, 119, 121, 124, 126, 135, 137, 139, 142, 144 agnd 98, 99, 100, 101, 102, 103, 104, 106 73 clockout 96 ~strobe ~writeenable 89 23 iointerrupt 52 47 pwmmag1b pwmsign1b 44 40 pwmmag1c pwmsign1c 56 54 pwmmag1a pwmsign1a 83 79 quada1 quadb1 ~parallelenable 8 69 ~index1 88 81 quadauxa1 quadauxb1 75 ~home1
mc58000 electrical specification ? preliminary 11/13/2003 33 5.1.1 mc58110 cp chip pin description cp pin name and number direction description ~reset 133 input this is the master reset signal. when brought low , this pin resets the chipset to its initial conditions. ~writeenable 89 output this signal is the write-enable strobe. when low , this signal indicates that data is being written to the bus. ~readenable 93 output this signal is the read-enable strobe. when low , this signal indicates that data is being read from the bus. ~strobe 96 output this signal is low when the data and address are valid during cp communications. if the parallel interface is used, this pin sh ould be connected to the pld/fpga io chip signal cpstrobe . r/~w 92 output this signal is high when the cp chip is performing a read, and low when it is performing a write. if the parallel interf ace is used, this pin should be connected to the pld/fpga io chip signal cpr/~w. w/~r 19 output this signal is the inverse of r/~w ; it is high when r/~w is low, and vice versa. for some decode circuits and devices this is more convenient than r/~w . ready 120 input ready can be pulled low to add wait states for external accesses. ready indicates that an external device is prepared for a bus transaction to be completed. if the device is not ready, it pulls the ready pin low . the motion processor then waits one cycle and checks ready again. this signal can be left unc onnected if it is not used. ~periphslct 82 output this signal is low when peripheral devices on the data bus are being addressed. if the parallel interface is used, this pin should be connected to the pld/fpga io chip signal cpperiphslct . ~ramslct 87 output this signal is low when external memory is being accessed. srlxmt 25 output this pin outputs serial data from the asynchronous serial port. srlrcv 26 input this pin inputs serial data to the asynchronous serial port. canxmt srlenable 72 output when the can host interface is used, this pin transmits serial data to the can transceiver. when the multi-drop serial interface is used , this pin sets the serial port enable line and the canxmt function is not available. srlenable is high during transmission for the multi-drop protocol and low at all other times. canrcv 70 output this pin receives serial data from the can transceiver. spiclock 35 output this pin is the clock signal used for strobing synchronous serial data to the serial dac(s). this signal is only active when spi data is being transmitted. spixmt 30 output this pin transmits synchronous serial data to the serial dac(s). iointerrupt 23 input this interrupt signal is used for io to cp communication. if the parallel interface is used, this pin should be connected to th e pld/fpga io chip signal cpinterrupt . this signal can be left unc onnected if it is not used. masterclkin 123 input this is the clock signal for the motion processor. it is driven at a nominal 20mhz. clockout 73 output this signal is the reference output clock. its frequency is twice the frequency of the input clock (which is normally 20mhz) resulting in a nominal output frequency of 40mhz.
mc58000 electrical specification ? preliminary 11/13/2003 34 cp pin name and number direction description addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 80 78 74 71 68 64 61 57 53 51 48 45 43 39 34 31 output multi-purpose address lines. these pins comprise the cp chip?s external address bus, used to select devices for communicat ion over the data bus. if the parallel interface is used, pins addr0 , addr1 , and addr15 should be connected to the pld/fpga io chip signals cpaddr0 , cpaddr1 and cpaddr15 . they are used to communicate between the cp and io chips. other address pins may be used for dac output, parallel word input, or user- defined i/o operations. see the user?s guide for a complete memory map. data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 127 130 132 134 136 138 143 5 9 13 15 17 20 22 24 27 bi-directional multi-purpose data lines. these pins comprise the cp chip?s external data bus, used for all communications with peripheral devices such as external memory or dacs. they may also be used for paralle l-word input and for user-defined i/o operations. if the parallel interface is used, these pi ns should be connected to the pld/fpga io chip signals cpdata0-15 . analogvcc 116 input analog input vcc. this pin should be connected to the analog input supply voltage, which must be in the range 3.0-3.6 v. if the analog input circuitry is not used, this pin should be tied to v cc . analogrefhigh 115 input analog high voltage reference fo r a/d input. the allowed range is analogreflow to analogvcc . if the analog input circuitry is not used, this pin should be tied to v cc . analogreflow 114 input analog low voltage reference fo r a/d input. the allowed range is analoggnd to analogrefhigh . if the analog input circuitry is not us ed, this pin should be tied to gnd. analoggnd 117 input analog input ground. this pin should be connected to the analog input power supply return. if the analog input circuitry is not us ed, this pin should be tied to gnd. analog0 analog1 analog2 analog3 analog4 analog5 analog6 analog7 112 113 110 111 107 109 105 108 input these signals provide general-purpose analog voltage levels which are sampled by an internal a/d converter. the a/d resolution is 10 bits. the allowed signal input range is analogreflow to analogrefhigh . any unused pins should be tied to analoggnd. if the analog input circuitry is not used , these pins should be tied to gnd.
mc58000 electrical specification ? preliminary 11/13/2003 35 cp pin name and number direction description poslim1 46 input this signal provides input from the positive-side (forward) travel limit switch. on power-up or after reset this signal defaults to active low interpretation, but the interpretation can be set to active high interpretation using the setsignalsense instruction. if this pin is not used it may be left unconnected. neglim1 38 input this signal provides input from the ne gative-side (reverse) tr avel limit switch. on power-up or after reset this signal defaults to active low interpretation, but the interpretation can be set to active high interpretation using the setsignalsense instruction. if this pin is not used it may be left unconnected. axisout1 32 output this pin can be programm ed to track the state of any bit in the status registers. if this pin is not used it may be left unconnected. axisin1 16 input this pin is a general-purpose input that can also be used as a breakpoint input. if this pin is not used it may be left unconnected. pwmmag1a pwmsign1a pwmmag1b pwmsign1b pwmmag1c pwmsign1c 56 54 52 47 44 40 output these pins provide th e pulse width modulated signals for each phase of the motor. the pwm resolution is 10 bits at a frequency of 20.0 khz or 80khz, selectable via the host command setpwmfrequency . in 2 or 3-phase pwm 50/50 mode, pw mmag1a/1b/1c are the only signals and encode both the magnitude and direction in the one signal. in single-phase pwm sign/magnitude mode, pwmmag1a and pwmsign1a are the pwm magnitude and direction signals respectively. in 2-phase pwm sign/magnitude mo de, pwmmag1a and pwmsign1a are the pwm magnitude and direction signals for phase a. pwmmag1b and pwmmag1b are the pwm magnitude and direction signals for phase b. unused pins should be left unconnected. refer to the user?s guide for more information on pwm encoding schemes. spienable1 54 output this pin provides the enable signal when spi dac output is active. the enable is high when the dac channel is being written to. at all other times the signal is low . spi output can only be used when the axis being controlled is dc brushed or when the amplifier expects a single-phase input and it perfor ms brushless motor commutation. pwm and step and direct ion output is not available when spi dac output is selected. if this pin is not used it may be left unconnected. pulse1 56 output this pin provides the pulse (step) sign al to the motor. a step occurs when the signal transitions from a high to a low state. this default behavior can be changed to a low to high state transition using the command setsignalsense . if this pin is not used it may be left unconnected. direction1 54 output this pin indicates the direction of motion and works in conjunction with the pulse signal. a high level on this signal indicates a positive direction move and a low level indicates a negative direction move. atrest1 52 output this signal indicates that the axis is at rest and the step motor can be switched to low power or standby mode. a high level on this signal indicates the axis is at rest while a low signal indicates the axis is in motion.
mc58000 electrical specification ? preliminary 11/13/2003 36 cp pin name and number direction description quada1 quadb1 83 79 input these pins should be connected to the a and b qu adrature signals from the incremental encoder. when the axis is moving in the positive (forward) direction, signal a leads signal b by 90. the theoretical maximum encoder pulse ra te is 5.0 mhz. actual maximum rate will vary, depending on signal noise. note : many encoders require a pull-up resistor on each signal to establish a proper high signal. check your encoder?s electrical specification. if these pins are not used th ey may be left unconnected. ~home1 75 input this pin provides the home signal , a general-purpose input to the position capture mechanism. a valid home signal is recognized by the motion processor when ~home transitions from high to low . if this pin is not used it may be left unconnected. quadauxa1 quadauxb1 ~index1 88 81 69 input if index capture is required, th e encoder a and b signals connected to quada1 and quadb1 signals must also be connected to quadauxa1 and quadauxb1 . the index pin should be c onnected to the index signal from the incremental encoder. a valid index pu lse is recognized by the motion processor when this signal transitions from high to low . if these pins are not used th ey may be left unconnected. warning! there is no internal gating of the index signal with the encoder a and b inputs. this must be performed externally if desired. refer to the application notes section at the end of this manual for an example. hall1a hall1b hall1c 18 14 37 input hall sensor inputs. these signals encode 6 valid states as follows: a on, a and b on, b on, b and c on, c on, c and a on. a sensor is defined as being on when its signal is high . on power-up or after reset these signal defaults to active high interpretation, but the interpretation can be set to active low interpretation using the setsignalsense instruction. note: these signals should only be conn ected to hall sensors that are mounted at a 120 offset. motors with hall signals 60 apart will not work. the number of available axes determines which of these signals are valid. if these pins are not used th ey may be left unconnected. parallelenable 8 input this signal enables/disables the para llel communication with the host. if this signal is tied high , the parallel interface is enable d. if this signal is tied low the parallel interface is disabled. contac t pmd for more information on parallel communication. warning! this signal should only be tied high if an external logic device that implements the parallel communication logic is included in the design. ~hostinterrupt 131 output when low , this signal causes an interrupt to be sent to the host processor. synch 21 input/output this pin is the synchronization signal. in the disabled mode, the pin is configured as an input and is not used. in the master mode, the pin outputs a synchronization pulse that can be used by slave nodes or other devices to synchronize with the internal chip cycle of the master node. in the slave mode, the pin is configured as an input and should be connected to the synch pin on the master node. a pulse on the pin synchr onizes the internal chip cycle to the signal provided by the master node. if this pin is not used it may be left unconnected. oscfilter1 oscfilter2 11 10 these signals connect to the external oscillator filter ci rcuitry. section 5.3 shows the required filter circuitry.
mc58000 electrical specification ? preliminary 11/13/2003 37 cp pin name and number direction description v cc5 58 this signal can optionally be tied to a 5v logic supply, which is required for reprogramming the chipset firmware. v ssf 12 this signal must be tied to pin 28 usin g a bypass capacitor. a ceramic capacitor with a value between 0.1f and 0.01f should be used. v cc 4, 29, 42, 50, 67, 77, 86, 95, 122, 129, 141 cp digital supply voltage. all of these pins must be connected to the supply voltage. v cc must be in the range 3.0 ? 3.6 v. gnd 3, 28, 41, 49, 66, 76, 85, 94, 125, 128, 140 cp digital supply ground. all of these pins must be connected to the digital power supply return. agnd 98, 99, 100, 101, 102, 103, 104, 106 these signals must be tied to analoggnd. if the analog input circuitry is not us ed, these pins must be tied to gnd. no connection 1, 2, 6, 7, 33, 36, 55, 59, 60, 62, 63, 65, 84, 90, 91, 97, 118, 119, 121, 124, 126, 135, 137, 139, 142, 144 these signals must be left unconnected. 5.1.2 mc58110 cp chip pin assignment for multiple motor types the mc58110 chip supports outp utting pwm motor commands in sign/magnitude and 50/50 modes. for stepping motors it can also output st ep and direction signals. the cp chip assigns pin function according to the selected output mode. if the output mode is set to pwm sign/magnitude , the following pinout should be used. pwmmag1a pwmmag1b 56 52 output these pins provide the pulse width modulated signal to the motor. in pwm 50/50 mode, this is the only signal. in pwm sign-magnitude mode, this is the magnitude signal. pwmsign1a pwmsign1b 54 47 output in pwm sign-magnitude mode, thes e pins provide the sign (direction) of the pwm signal to the motor amplifier. if the output mode is set to pwm 5050 , the following pinout should be used. pwmmag1a pwmmag1b pwmmag1c 56 52 44 output these pins provide the pulse width modulated signals for each phase to the motor. if the number of phases is 2, only phase a and b are valid. if the number of phases is 3, phases a,b and c are valid. the number of phases is set using the command setnumberphases . in pwm 50/50 mode, these are the only signals. if the output mode is set to step and direction , the following pinout should be used. pulse1 56 output this pin provides the pulse (step) signal to the motor. direction1 54 output these pin indicates the directi on of motion and works in conjunction with the pulse signal. atrest1 52 output this signal indicates the axis is at rest and the step motor can be switched to low power or standby mode. if the output mode is set to spi dac , the following pinout should be used. spienable1 54 output this pin provides the enable si gnal when spi dac output is active.
mc58000 electrical specification ? preliminary 11/13/2003 38 5.2 pinouts for the mc58420 io vcc 16, 17, 40, 65, 66, 67, 90 cp ~readenable ~periphslct 81 8 92 100 94 cpdata8 cpdata9 cpdata10 cpdata11 cpdata12 cpdata13 cpdata14 cpdata15 hostcmd hostrdy ~hostread ~hostwrite ~hostslct 12 10 99 98 1 11 97 95 76 74 73 75 2 3 7 6 38 36 35 32 31 37 42 39 hostdata0 hostdata1 hostdata2 hostdata3 hostdata4 hostdata5 hostdata6 hostdata7 hostdata8 hostdata9 hostdata10 hostdata11 hostdata12 hostdata13 hostdata14 hostdata15 cpdata0 cpdata1 cpdata2 cpdata3 cpdata4 cpdata5 cpdata6 cpdata7 18 14 71 13 70 15 69 68 21 85 20 79 77 53 54 52 41 43 50 89 24 5 91 pwmmag1a pwmmag2a pwmmag3a pwmmag4a cpinterrupt cpr/~w cpstrobe cpperiphslct cpaddr0 cpaddr1 cpaddr15 cpclock masterclkin hostmode0 hostmode1 47 25 49 82 48 44 93 29 33 51 83 88 30 58 28 45 quada1 quadb1 ~index1 ~home1 quada2 quadb2 ~index2 ~home2 quada3 quadb3 ~index3 ~home3 quada4 quadb4 ~index4 ~home4 127 130 132 134 136 138 143 5 9 13 15 17 20 22 24 27 80 78 74 71 68 64 61 57 53 51 48 45 43 39 34 31 25 26 72 70 23 123 srlxmt srlrcv canxmt/srlenable canrcv iointerrupt ioclock data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 92 120 82 87 133 r/~w ready ~ramslct ~reset 19 93 46 59 65 81 38 55 62 69 poslim1 poslim2 poslim3 poslim4 neglim1 neglim2 neglim3 neglim4 115 114 117 32 119 88 54 16 8 52 83 axisout1 axisout2 axisout3 axisout4 axisin1 axisin2 axisin3 axisin4 analogvcc analogrefhigh analogreflow analoggnd 116 hall1a hall2a hall3a hall4a hall1b hall1c hall2c hall2b hall3c hall3b hall4b hall4c 6 18 14 37 2 126 47 44 56 79 75 40 pwmmag1b pwmmag1c pwmmag2b pwmmag2c pwmmag3b pwmmag3c pwmmag4b pwmmag4c 23 62 87 86 19 63 78 80 59 61 26 pwmsign1 pwmsign4 pwmsign3 pwmsign2 60 w/~r ~hostinterrupt 131 synch 21 vssf 12 oscfilter1 11 oscfilter2 10 vcc5 58 vcc 4, 29, 42, 50, 67, 77, 86, 95, 122, 129, 141 112 113 110 111 107 109 105 108 analog0 analog1 analog2 analog3 analog4 analog5 analog6 analog7 35 30 spiclock spixmt gnd 3, 28, 41, 49, 66, 76, 85, 94, 125, 128, 140 no connection 1, 7, 33, 36, 60, 63, 84, 90, 91, 97, 118, 121, 124, 135, 137, 139, 142, 144 gnd 4, 9, 22, 34, 46, 57, 64, 72, 84, 96 no connection 27, 55, 56 agnd 98, 99, 100, 101, 102, 103, 104, 106 73 clockout 96 ~strobe ~writeenable 89
mc58000 electrical specification ? preliminary 11/13/2003 39 5.2.1 mc58020 io chip pin description io pin name and number direction description hostcmd 81 input this signal is asserted high to write a host instruction to the motion processor, or to read the status of the hostrdy and hostinterrupt signals. it is asserted low to read or write a data word. hostrdy 8 output this signal is used to sync hronize communication between the motion processor and the host. hostrdy (hostready) will go low indicating host port busy at the end of a read or write operation according to the interface mode in use, as follows: interface mode hostrdy goes low 8/16 after the second byte of the instruction word after the second byte of each data word is transferred 16/16 after the 16-bit instruction word after each 16-bit data word hostrdy will go high, indicating that the host port is ready to transmit, when the last transmission has b een processed. all host port communications must be made with hostrdy high (ready). a typical busy-to-ready cyc le is 10 microseconds, bu t can be substantially longer, up to 50 microseconds. ~hostread 92 input when ~hostread is low , a data word is read fr om the motion processor. ~hostwrite 100 input when ~hostwrite is low , a data word is written to the motion processor. ~hostslct 94 input when ~hostslct is low , the host port is selected for reading or writing operations. cpinterrupt 77 output io chip to cp chip interrupt. it should be connected to cp chip pin 23, iointerrupt . cpr/~w 53 input this signal is high when the cp chip is reading data from the io chip, and low when it is writing data. it shou ld be connected to cp chip pin 92, r/~w . cpstrobe 54 input this signal goes low when the data and address become valid during motion processor communication with peripheral devices on the data bus, such as external memory or a dac. it should be connected to cp chip pin 96, ~strobe . cpperiphslct 52 input this signal goes low when a peripheral device on the data bus is being addressed. it should be c onnected to cp chip pin 82, ~periphslct. cpaddr0 cpaddr1 cpaddr15 41 43 50 input these signals are high when the cp chip is communicating with the io chip (as distinguished from any ot her device on the data bus). they should be connected to cp chip pins 80 ( addr0 ), 78 ( addr1 ), and 31 ( addr15 ). masterclkin 89 input this is the master clock signal for the motion processor. it is driven at a nominal 40 mhz cpclock 24 output this signal provides the clock puls e for the cp chip. its frequency is half that of masterclkin (pin 89), or 20 mhz nominal. it is connected directly to the cp chip ioclock signal (pin 123). hostmode0 hostmode1 5 91 input these two signals determine the host communications mode, as follows: hostmode1 hostmode0 0 0 16/16 parallel (16-bit bus, 16-bit instruction) 0 1 not used 1 0 8/16 parallel (8-bit bus, 16-bit instruction) 1 1 parallel disabled
mc58000 electrical specification ? preliminary 11/13/2003 40 io pin name and number direction description hostdata0 hostdata1 hostdata2 hostdata3 hostdata4 hostdata5 hostdata6 hostdata7 hostdata8 hostdata9 hostdata10 hostdata11 hostdata12 hostdata13 hostdata14 hostdata15 12 10 99 98 1 11 97 95 76 74 73 75 2 3 7 6 bi-directional, tri-state these signals transmit data between the host and the motion processor through the parallel port. transmission is mediated by the control signals ~hostselect, ~hostwrite, ~hostread and hostcmd . in 16-bit mode, all 16 bits are used ( hostdata0-15 ). in 8-bit mode, only the low-order 8 bits of data are used ( hostdata0-7 ). the hostmode0 and hostmode1 signals select the communication mode this port operates in. cpdata0 cpdata1 cpdata2 cpdata3 cpdata4 cpdata5 cpdata6 cpdata7 cpdata8 cpdata9 cpdata10 cpdata11 cpdata12 cpdata13 cpdata14 cpdata15 38 36 35 32 31 37 42 39 18 14 71 13 70 15 69 68 bi-directional these signals transmit data between the io chip and pins data0-15 of the cp chip. pwmmag1a pwmmag1b pwmmag1c pwmsign1a 21 62 23 61 output these pins provide the pulse width modulated signals for each phase of the motor. the pwm resolution is 10 bits at a frequency of 20.0 khz or 80khz, selectable via the host command setpwmfrequency. these pins control axis 1. in 2 or 3-phase pwm 50/50 mode , pwmmag1a/1b/1c are the only signals and encode both the magnitude and direction in the one signal. in single-phase pwm sign/m agnitude mode, pwmmag1a and pwmsign1a are the pwm magnitude and direction signals respectively. in 2-phase pwm sign/magnitude mode, pwmmag1a and pwmsign1a are the pwm magnitude and directi on signals for phase a. pwmmag1b and pwmmag1c, ?pwmsign1b?, are the pwm magnitude and direction signals for phase b. the number of available axes determines which of these signals are valid. unused pins should be left unconnected. refer to the user?s guide for more information on pwm encoding schemes.
mc58000 electrical specification ? preliminary 11/13/2003 41 io pin name and number direction description pwmmag2a pwmmag2b pwmmag2c pwmsign2a 85 87 86 60 output these pins control axis 2. in 2 or 3-phase pwm 50/50 mode , pwmmag2a/2b/2c are the only signals and encode both the magnitude and direction in the one signal. in single-phase pwm sign/m agnitude mode, pwmmag2a and pwmsign2 are the pwm magnitude and direction signals respectively. in 2-phase pwm sign/magnitude mode, pwmmag2a and pwmsign2a are the pwm magnitude and directi on signals for phase a. pwmmag2b and pwmmag2c, ?pwmsign2b?, are the pwm magnitude and direction signals for phase b. the number of available axes determines which of these signals are valid. unused or invalid pins shou ld be left unconnected. pwmmag3a pwmmag3b pwmmag3c pwmsign3a 20 19 63 59 output these pins control axis 3. in 2 or 3-phase pwm 50/50 mode , pwmmag3a/3b/3c are the only signals and encode both the magnitude and direction in the one signal. in single-phase pwm sign/m agnitude mode, pwmmag3a and pwmsign3a are the pwm magnitude and direction signals respectively. in 2-phase pwm sign/magnitude mode, pwmmag3a and pwmsign3a are the pwm magnitude and directi on signals for phase a. pwmmag3b and pwmmag3c, ?pwmsign3b?, are the pwm magnitude and direction signals for phase b. the number of available axes determines which of these signals are valid. unused or invalid pins shou ld be left unconnected. pwmmag4a pwmmag4b pwmmag4c pwmsign4a 79 78 80 26 output these pins control axis 4. in 2 or 3-phase pwm 50/50 mode , pwmmag4a/4b/4c are the only signals and encode both the magnitude and direction in the one signal. in single-phase pwm sign/m agnitude mode, pwmmag4a and pwmsign4a are the pwm magnitude and direction signals respectively. in 2-phase pwm sign/magnitude mode, pwmmag4a and pwmsign4a are the pwm magnitude and directi on signals for phase a. pwmmag4b and pwmmag4c, ?pwmsign4b?, are the pwm magnitude and direction signals for phase b. the number of available axes determines which of these signals are valid. unused or invalid pins shou ld be left unconnected.
mc58000 electrical specification ? preliminary 11/13/2003 42 io pin name and number direction description spienable1 spienable2 spienable3 spienable4 21 85 20 79 output these pins provide the enable si gnal when spi dac output is active. each enable is high when the specific dac channel is being written to. at all other times the signals are low . there is one signal per axis. spi outp ut can only be used when the axis being controlled is dc brushed or when the amplifier expects a single- phase input and it performs brushless motor commutation. the number of available axes determines which of these signals are valid. unused or invalid pins shou ld be left unconnected. pulse1 pulse2 pulse3 pulse4 21 85 20 79 output these pins provide th e pulse (step) signal to the motor. this signal is always a square wave, regardless of the pulse rate. a step occurs when the signal transitions from a high state to a low state. this default behavior can be changed to a low to high state transition using the command setsignalsense. the number of available axes determines which of these signals are valid. invalid axis pins may be left unconnected. direction1 direction2 direction3 direction4 61 60 59 26 output these pins indicate the direction of motion and work in conjunction with the pulse signal. a high level on this signal indicates a positive direction move and a low level indicates a negative direction move. the number of available axes determines which of these signals are valid. invalid axis pins may be left unconnected. atrest1 atrest2 atrest3 atrest4 23 86 63 80 output the atrest signal indicates the axis is at rest and the step motor can be switched to low power or standby. a high level on this signal indicates the axis is at rest. a low signal indicates the axis is in motion. the number of available axes determines which of these signals are valid. invalid axis pins may be left unconnected. quada1 quadb1 quada2 quadb2 quada3 quadb3 quada4 quadb4 47 25 48 44 33 51 30 58 input these pins provide the a and b quadrature signals for the incremental encoder for each axis. when the axis is moving in the positive (forward) direction, signal a leads signal b by 90. the theoretical maximum encoder pulse rate is 10.2 mhz. actual maximum rate will vary, depending on signal noise. note : many encoders require a pull-up resistor on each signal to establish a proper high signal. check your encoder?s electrical specification. the number of available axes determines which of these signals are valid. warning! if a valid axis pin is not used, its signal should be tied high. invalid axis pins may be left un connected or conne cted to ground. ~index1 ~index2 ~index3 ~index4 49 93 83 28 input these pins provide the index quadrature signals for the incremental encoders. a valid index pulse is recognized by the chipset when ~index , a , and b are all low . the number of available axes determines which of these signals are valid. warning! if a valid axis pin is not used, its signal should be tied high. invalid axis pins may be left un connected or conne cted to ground.
mc58000 electrical specification ? preliminary 11/13/2003 43 io pin name and number direction description ~home1 ~home2 ~home3 ~home4 82 29 88 45 input these pins provide the home sign als, general-purpose inputs to the position-capture mechanism. a valid ho me signal is recognized by the chipset when ~home n goes low . these signals are similar to ~index , but are not gated by the a and b encoder channels. the number of available axes determines which of these signals are valid. warning! if a valid axis pin is not used, its signal should be tied high. invalid axis pins may be left un connected or conne cted to ground. vcc 16, 17, 40, 65, 66, 67, 90 all of these pins must be connected to the io chip digital supply voltage, which should be in the range 3.0 to 3.6 v. gnd 4, 9, 22, 34, 46, 57, 64, 72, 84, 96 io chip ground. all of these pins must be connected to the digital power supply return. not connected 27, 55, 56 these pins must be left unconnected (floating).
mc58000 electrical specification ? preliminary 11/13/2003 44 5.2.2 mc58020 io chip pin assignment for multiple motor types the mc58020 chip supports outp utting pwm motor commands in sign/magnitude and 50/50 modes. for stepping motors it can also output st ep and direction signals. the io chip assigns pin function according to the selected output mode. for axis 1 of the chipset: if the output mode is set to pwm sign/magnitude , the following pinout should be used. pwmmag1a pwmmag1b 21 62 output these pins provide the pulse width modulated signal to the motor. in pwm 50/50 mode, this is the only signal. in pwm sign-magnitude mode, this is the magnitude signal. pwmsign1a pwmsign1b 61 23 output in pwm sign-magnitude mode, thes e pins provide the sign (direction) of the pwm signal to the motor amplifier. if the output mode is set to pwm 5050 , the following pinout should be used. pwmmag1a pwmmag1b pwmmag1c 21 62 23 output these pins provide the pulse width modulated signals for each phase to the motor. if the number of phases is 2, only phase a and b are valid. if the number of phases is 3, phases a,b and c are valid. the number of phases is set using the motion pr ocessor command se tnumberphases. in pwm 50/50 mode, these are the only signals. if the output mode is set to step and direction , the following pinout should be used. pulse1 21 output this pin provides the pulse (step) signal to the motor. direction1 61 output these pin indicates the directi on of motion and works in conjunction with the pulse signal. atrest1 23 output this signal indicates the axis is at rest and the step motor can be switched to low power or standby. for axis 2 of the chipset: if the output mode is set to pwm sign/magnitude , the following pinout should be used. pwmmag2a pwmmag2b 85 87 output these pins provide the pulse width modulated signal to the motor. in pwm 50/50 mode, this is the only signal. in pwm sign-magnitude mode, this is the magnitude signal. pwmsign2a pwmsign2b 60 86 output in pwm sign-magnitude mode, thes e pins provide the sign (direction) of the pwm signal to the motor amplifier. if the output mode is set to pwm 5050 , the following pinout should be used. pwmmag2a pwmmag2b pwmmag2c 85 87 86 output these pins provide the pulse width modulated signals for each phase to the motor. if the number of phases is 2, only phase a and b are valid. if the number of phases is 3, phases a,b and c are valid. the number of phases is set using the motion pr ocessor command se tnumberphases. in pwm 50/50 mode, these are the only signals. if the output mode is set to step and direction , the following pinout should be used. pulse2 85 output this pin provides the pulse (step) signal to the motor. direction2 60 output these pin indicates the directi on of motion and works in conjunction with the pulse signal. atrest2 86 output this signal indicates the axis is at rest and the step motor can be switched to low power or standby.
mc58000 electrical specification ? preliminary 11/13/2003 45 for axis 3 of the chipset: if the output mode is set to pwm sign/magnitude , the following pinout should be used. pwmmag3a pwmmag3b 20 19 output these pins provide the pulse width modulated signal to the motor. in pwm 50/50 mode, this is the only signal. in pwm sign-magnitude mode, this is the magnitude signal. pwmsign3a pwmsign3b 59 63 output in pwm sign-magnitude mode, thes e pins provide the sign (direction) of the pwm signal to the motor amplifier. if the output mode is set to pwm 5050 , the following pinout should be used. pwmmag3a pwmmag3b pwmmag3c 20 19 63 output these pins provide the pulse width modulated signals for each phase to the motor. if the number of phases is 2, only phase a and b are valid. if the number of phases is 3, phases a,b and c are valid. the number of phases is set using the motion pr ocessor command se tnumberphases. in pwm 50/50 mode, these are the only signals. if the output mode is set to step and direction , the following pinout should be used. pulse3 20 output this pin provides the pulse (step) signal to the motor. direction3 59 output these pin indicates the directi on of motion and works in conjunction with the pulse signal. atrest3 63 output this signal indicates the axis is at rest and the step motor can be switched to low power or standby. for axis 4 of the chipset: if the output mode is set to pwm sign/magnitude , the following pinout should be used. pwmmag4a pwmmag4b 79 78 output these pins provide the pulse width modulated signal to the motor. in pwm 50/50 mode, this is the only signal. in pwm sign-magnitude mode, this is the magnitude signal. pwmsign4a pwmsign4b 26 80 output in pwm sign-magnitude mode, thes e pins provide the sign (direction) of the pwm signal to the motor amplifier. if the output mode is set to pwm 5050 , the following pinout should be used. pwmmag4a pwmmag4b pwmmag4c 79 78 80 output these pins provide the pulse width modulated signals for each phase to the motor. if the number of phases is 2, only phase a and b are valid. if the number of phases is 3, phases a,b and c are valid. the number of phases is set using the motion pr ocessor command se tnumberphases. in pwm 50/50 mode, these are the only signals. if the output mode is set to step and direction , the following pinout should be used. pulse4 79 output this pin provides the pulse (step) signal to the motor. direction4 26 output these pin indicates the directi on of motion and works in conjunction with the pulse signal. atrest4 80 output this signal indicates the axis is at rest and the step motor can be switched to low power or standby. any unused pins may be le ft unconnected (floating).
mc58000 electrical specification ? preliminary 11/13/2003 46 5.2.3 mc58020 cp chip pin description cp pin name and number direction description ~reset 133 input this is the master reset signal. when brought low , this pin resets the chipset to its initial conditions. ~writeenable 89 output this signal is the write-enable strobe. when low , this signal indicates that data is being written to the bus. ~readenable 93 output this signal is the read-enable strobe. when low , this signal indicates that data is being read from the bus. ~strobe 96 output this signal is low when the data and address are valid during cp communications. it should be connected to io chip pin 54, cpstrobe . r/~w 92 output this signal is high when the cp chip is performing a read, and low when it is performing a write. it should be connected to io chip pin 53, cpr/~w. w/~r 19 output this signal is the inverse of r/~w ; it is high when r/~w is low, and vice versa. for some decode circuits and devices this is more convenient than r/~w . ready 120 input ready can be pulled low to add wait states for external accesses. ready indicates that an external device is prepared for a bus transaction to be completed. if the device is not ready, it pulls the ready pin low . the motion processor then waits one cycle and checks ready again. this signal can be left unc onnected if it is not used. ~periphslct 82 output this signal is low when peripheral devices on the da ta bus are being addressed. it should be connected to io chip pin 52, cpperiphslct . ~ramslct 87 output this signal is low when external memory is being accessed. srlxmt 25 output this pin outputs serial data from the asynchronous serial port. srlrcv 26 input this pin inputs serial data to the asynchronous serial port. canxmt srlenable 72 output when the can host interface is used, this pin transmits serial data to the can transceiver. when the multi-drop serial interface is used , this pin sets the serial port enable line and the canxmt function is not available. srlenable is high during transmission for the multi-drop protocol and low at all other times. canrcv 70 output this pin receives serial data from the can transceiver. spiclock 35 output this pin is the clock signal used for strobing synchronous serial data to the serial dac(s). this signal is only active when spi data is being transmitted. spixmt 30 output this pin transmits synchronous serial data to the serial dac(s). iointerrupt 23 input this interrupt signal is used for io to cp communication. it should be connected to io chip pin 77, cpinterrupt . ioclock 123 input this is the cp chip clock signal. it should be connected to io chip pin 24, cpclock . clockout 73 output this signal is the reference output clock. its frequency is the same as the masterclkin signal to the io chip, nominally 40mhz.
mc58000 electrical specification ? preliminary 11/13/2003 47 cp pin name and number direction description addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 80 78 74 71 68 64 61 57 53 51 48 45 43 39 34 31 output multi-purpose address lines. these pins comprise the cp chip?s external address bus, used to select devices for communication over the data bus. addr0 , addr1 , and addr15 are connected to the corresponding cpaddr pins on the io chip, and are used to communicate between the cp and io chips. other address pins may be used for dac output, parallel word input, or user- defined i/o operations. see the user?s guide for a complete memory map. data0 data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 127 130 132 134 136 138 143 5 9 13 15 17 20 22 24 27 bi-directional multi-purpose data lines. these pins comprise the cp chip?s external data bus, used for all communications with the io chip and peripheral devices such as external memory or dacs. they may also be used fo r parallel-word input and for user-defined i/o operations. analogvcc 116 input analog input vcc. this pin should be connected to the analog input supply voltage, which must be in the range 3.0-3.6 v. if the analog input circuitry is not used, this pin should be tied to v cc . analogrefhigh 115 input analog high voltage reference fo r a/d input. the allowed range is analogreflow to analogvcc . if the analog input circuitry is not used, this pin should be tied to v cc . analogreflow 114 input analog low voltage reference fo r a/d input. the allowed range is analoggnd to analogrefhigh . if the analog input circuitry is not us ed, this pin should be tied to gnd. analoggnd 117 input analog input ground. this pin should be connected to the analog input power supply return. if the analog input circuitry is not us ed, this pin should be tied to gnd. analog0 analog1 analog2 analog3 analog4 analog5 analog6 analog7 112 113 110 111 107 109 105 108 input these signals provide general-purpose analog voltage levels which are sampled by an internal a/d converter. the a/d resolution is 10 bits. the allowed signal input range is analogreflow to analogrefhigh . any unused pins should be tied to analoggnd. if the analog input circuitry is not used , these pins should be tied to gnd.
mc58000 electrical specification ? preliminary 11/13/2003 48 cp pin name and number direction description poslim1 poslim2 poslim3 poslim4 46 59 65 81 input these signals provide inputs from the positive-si de (forward) travel limit switches. on power-up or after rese t these signals default to active low interpretation, but the interpretation can be set explicitly using the setsignalsense instruction. the number of available axes determines which of these signals are valid. invalid or unused pins ma y be left unconnected. neglim1 neglim2 neglim3 neglim4 38 55 62 69 input these signals provide inputs from the negative-side (reverse) travel limit switches. on power-up or after re set these signals default to active low interpretation, but the interpretation can be set explicitly using the setsignalsense instruction. the number of available axes determines which of these signals are valid. invalid or unused pins ma y be left unconnected. axisout1 axisout2 axisout3 axisout4 32 119 88 54 output each of these pins can be conditioned to track the state of any bit in the status registers associated with its axis. the number of available axes determines which of these signals are valid. invalid or unused pins ma y be left unconnected. axisin1 axisin2 axisin3 axisin4 16 8 52 83 input these are general- purpose inputs that can also be used as a breakpoint input. the number of available axes determines which of these signals are valid. invalid or unused pins ma y be left unconnected. hall1a hall1b hall1c hall2a hall2b hall2c hall3a hall3b hall3c hall4a hall4b hall4c 18 14 37 6 2 126 47 44 40 79 75 56 input hall sensor inputs. each set (a, b, an d c) of signals encodes 6 valid states as follows: a on, a and b on, b on, b and c on, c on, c and a on. a sensor is defined as being on when its signal is high . note: these signals should only be conn ected to hall sensors that are mounted at a 120 offset. motors with hall signals 60 apart will not work. the number of available axes determines which of these signals are valid. invalid or unused pins ma y be left unconnected. ~hostinterrupt 131 output when low , this signal causes an interrupt to be sent to the host processor. synch 21 input/output this pin is the synchronization signal. in the disabled mode, the pin is configured as an input and is not used. in the master mode, the pin outputs a synchronization pulse that can be used by slave nodes or other devices to synchronize with the internal chip cycle of the master node. in the slave mode, the pin is configured as an input and should be connected to the synch pin on the master node. a pulse on the pin synchr onizes the internal chip cycle to the signal provided by the master node. if this pin is not used it may be left unconnected. oscfilter1 oscfilter2 11 10 these signals connect to the external oscillator filter ci rcuitry. section 5.3 shows the required filter circuitry. v cc5 58 this signal can optionally be tied to a 5v logic supply, which is required for reprogramming the chipset firmware. v ssf 12 this signal must be tied to pin 28 usin g a bypass capacitor. a ceramic capacitor with a value between 0.1f and 0.01f should be used. v cc 4, 29, 42, 50, 67, 77, 86, 95, 122, 129, 141 cp digital supply voltage. all of these pins must be connected to the supply voltage. v cc must be in the range 3.0 ? 3.6 v. gnd 3, 28, 41, 49, 66, 76, 85, 94, 125, 128, 140 cp digital supply ground. all of these pins must be connected to the digital power supply return. agnd 98, 99, 100, 101, 102, 103, 104, 106 these signals must be tied to analoggnd. if the analog input circuitry is not us ed, these pins must be tied to gnd.
mc58000 electrical specification ? preliminary 11/13/2003 49 cp pin name and number direction description no connection 1, 7, 33, 36, 60, 63, 84, 90, 91, 97, 118, 121, 124, 135, 137, 139, 142, 144 these signals must be left unconnected.
mc58000 electrical specification ? preliminary 11/13/2003 50 5.3 external oscillator filter the following circuit shows the recommended config uration and suggested values for the filter that must be connected to the oscfilter1 and oscfilter2 pi ns of the cp chip. the resistor tolerance is 5% and the capacitor tolerance is 20%. c1 .15uf oscfilter1 r1 24ohm oscfilter2 c2 .0033uf

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